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| smh4814 preliminary information 1 (see last page) ? summit microelectronics, inc. 2005 ? 1717 fox drive ? san jose ca 95131 ? phone 408 436-9890 ? fax 408 436-9897 the summit web site can be accessed by ?right ? or ?left? mouse clicking on the link: http://www.summitmicro.com/ 2080 2.0 07/21/05 1 dual feed active-oring progr ammable hot swap controller features and applications eliminates passive oring diodes for reduced power consumption high noise immunity on all logic inputs soft starts main power supply on card insertion or system power up with slew rate control programmable differential current sense ? programmable inrush current limiting ? master enable to allo w system control of power-up or -down programmable independent enabling of up to 4 dc/dc converters programmable circuit breaker level and mode programmable quick-trip? value, current limiting, duty cycle times, over-current filter programmable host voltage fault monitoring programmable uv/ov filter and hysteresis programmable fault mode: latched or duty cycle internal shunt regulator allows for a wide supply range applications telecom hot-swap card - advancedtca tm network processors power-on ethernet, ieee 802.3af introduction the smh4814 is an integrated power controller designed to control the hot-swapping of plug-in cards in a distributed power environment. the smh4814 drives external power mosfet switches that connect the supply to the load while reducing in-rush current and providing over-current protection. when the source and drain voltages of the external mosfets are within specification t he smh4814 asserts the four pup logic outputs in a programmable cascade sequence to enable the dc/dc converters. the smh4814 also monitors two independent ?48v feeds. the redundant power supplies allow for high availability and reliability. the traditional method of supplying power from these feeds is via oring power diodes, which consume a significant amount of power. the smh4814 allows low-rds on fets to be used in place of oring diodes to reduce power consumption. the smh4814 determines when at least one of the ?48v feeds is within an acceptable voltage range and switches on the appropriate fet path while providing slew rate control. the smh4814 continuously monitors the incoming feeds and switch es to the most negative feed as necessary. the smh4814 is programmed and controlled using the i 2 c bus as required in atca tm applications. ?48v ret. r d uv ov vss v12 smh4814 feed a feed b vgate a vgate b cbsense ?48v a ?48v b pup a pup b pup c pup d vgate_hs drain sense v in + v out + v out - v in - on/off fb a fb b fb c fb d primary secondary r s pd0 pd1 pin detect pin detect scl sda i 2 c dc-to-dc converter a r a r b figure 1. the smh4814 controller hot-swaps and cascade sequences up to 4 dc/dc converters and actively controls the a and b ?48v feeds eliminating the need for oring diodes and the associated voltage drop. note: this is an applications example only. some pins, components and values are not shown. simplified applications drawing a dvanced t c a tm
smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 2 general description the smh4814 integrated pow er controller operates within a wide supply range, typically ?32 to ?72 volts, and generates the signals neces sary to drive isolated- output dc/dc converters. the device accepts two i ndependent ?48v feeds via input pins feed a and feed b . the vgate a pin controls the flow of power from feed a to the load. the vgate b pin controls the flow of power from feed b to the load. the smh4814 continuously monitors the voltage on feed a and feed b . the supply arbitration block in figure 2 selects which pin dr ives power to the device based on the voltage level on each pin and the acceptable voltage range. once the feed a or feed b pin is selected the smh4814 asserts the corresponding vgate pin. the assertion of this pin turns on the external low-rds on fets to supply power to the load. start-up procedure the general start-up procedure is as follows: 1. a physical connection must be made with the chassis to discharge any electrostatic voltage potentials when a typical add-in board is inserted into the powered backplane. 2. the board then contacts the long pins on the backplane that provide power and ground. 3. as soon as power is applied the device starts up, but it does not immediately apply power to the output load. 4. under-voltage and over-voltage circuits inside the controller verify that the input voltage is within a user-specified range. 5. the smh4814 senses the pd1 and pd0 pin detection signals to indicate the card is seated properly. these requirements must be met for a pin detect delay period of t pdd . once this time has elapsed the hot-swap controller enables vgate_hs to turn on the external power mosfet switch. the vgate_hs output is current limited to i vgate , allowing the slew rate to be easily modified using external passive components. during the controlled turn-on period the v ds of the mosfet is monitored by the drain sense input. when drain sense drops below 2.5v, and vgate_hs rises above v12 ? v gt , the smh4814 asserts the pup a through pup d power good outputs to enable the dc/dc controllers. steady-state operation is maintained as long as all conditions are normal. any of the following events may cause the device to disable the dc/dc controllers by shutting down the power mosfets: an under-voltage or over-voltage condition on the host power supply. a failure of the power mosfet sensed via the drain sense pin. the pd1/pd0 pin detect signals becoming invalid. the master enable (en/ts) falls below 2.5v. any of the fb inputs driv en low by events on the secondary side of the dc/dc controllers. the occurrence of an overcurrent. the smh4814 may be configured so that after any of these events occurs the vgate output shuts off, and either latches into an off state or recycles power after a cooling down period, t cyc . powering v12 the smh4814 contains an internal shunt regulator on the v12 pin that prevents the voltage from exceeding 12v. it is necessary to use a dropping resistor (r d ) between the host power supply and the v12 pin in order to limit current into the device and prevent possible damage. the dropping resistor allows the device to operate across a wide range of system supply voltages, typically ?32 v to ?72v, and also helps protect the device against common-mode power surges. refer to the applications section for help on calculating the r d resistance value. smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 3 voltage regulator and reference generator v12 5v_cap cb sense and gate control cbsense slew drain_sense vgate_hs e 2 memory configuration, status, and command registers i2c interface virtual address a2, a1 scl sda ents + - 2.5v ref pd0 pd1 + - prog ref uv prog hyst + - prog ref ov prog hyst glitch filter uv/ov filter po filter glitch filter reset# fault latch duty cycle timer fault# pup a polarity pup a fb a pup b polarity pup b fb b pup c polarity pup c fb c pup d polarity pup d fb d time slot and pup control feed a feed b gate a gate b supply arbitration programmable fault conditions figure 2. block diagram internal functional block diagram smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 4 pin description pin no. qfn pin type name description 1,2 i pd0, pd1 the pd pins are active high, logic level inputs. protection diodes allow them to be overdriven when used in conjunction with a series limiting resistor. the pd pins have an internal pull-down current sink of 10ua typical. 3 i reset# the reset# pin is used to clear latched fault conditions. when this pin is asserted, the vgate x and pup x outputs are immediately disabled. refer to the section on circuit breaker operation for more information. the reset# pin has an internal pull-up current source to 5v_cap of 10ua typical. 4 i scl scl is the serial clock input. 5 i/o sda sda is the bidirectional serial data i/o port. 6, 7, 8, 9 o pup a , pup b , pup c , pup d the pup x outputs are programmable acti ve high/low open drain converter enable pins. they can be used in one of 4 programmable sequence positions to switch a load or enable a dc/dc converter after a programmable delay, t pgdn . the voltage on these pins cannot exceed 12v relative to v ss . 10 o fault# fault# is an open-drain, active-low output that indicates the fault status of the device. the device?s status regi ster may be polled to determine more detailed information about the fault condition. 11 pwr vss this is connected to the negative side of the supply. 12 i cbsense the circuit breaker sense input is us ed to detect over-current conditions across an external, low value sense resistor (r s ) tied in series with the power mosfet. a voltage drop of greater than v cb (programmable level) across the resistor for longer than t cbd trips the circuit breaker. a programmable quick-trip? sense point is also available. 13 i uv the uv pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. vgate_hs is enabled when the uv input > vuv and disabled when uv < vuv-vuvhys. an optional programmable filter delay is also available on the uv input. 14 i ov the ov pin is used as an over-voltage supply monitor, typically in conjunction with an external resistor ladder. vgate_hs is disabled when ov > vov and enabled when ov < vov-vovhys. a filter delay is also available on the ov input. 15 i en/ts the enable/temperature sense input is the master enable input. if en/ts is less than 2.5v, all vgate outputs are disabled. 16 i slew_cntl a capacitor connected to this pin c ontrols the vgate_hs slew rate. 17 i feed b connect to the -48v 'b' feed using a series 100k resistor. the voltage on this pin is compared with the voltage on the feed a pin internally by the supply arbitration logic to determine which voltage will be used. smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 5 pin description (continued) pin no. qfn pin type name description 18 i feed a connect to the -48v 'a' feed using a series 100k resistor. the voltage on this pin is compared with the voltage on the feed b pin internally by the supply arbitration logic to determine which voltage will be used. 19 i drain sense the drain sense input monitors the voltage at the drain of the external power mosfet switch with respect to vss. an internal 10a source pulls the drain sense signal towards the 5v_cap level. drain sense must be held below 2.5v to enable the pup x outputs. 20 o 5v_cap external capacitor input used to filter the device?s internal operating supply. also a hold capacitor to sequence down and to filter any power glitches. 21 o vgate_hs the vgate_hs output activates an external power mosfet switch. this signal controls inrush current by modulating the gate of the hot swap mosfet device. it supplies a programmable current output which allows easy adjustment of the mosfet turn-on slew rate. 22 o vgate b this pin controls the gate of the active fet on feed b . 23 o vgate a this pin controls the gate of the active fet on feed a 24 pwr v12 this is the positive supply input. an internal shunt regulator limits the voltage on this pin to approximately 12v with respect to v ss . a resistor must be placed in series with the v12 pin to limit the regulator current (r d in the application schematics). 25 i fb d active-high, logic level input that can be used to indicate when the converter controlled by pup d is fully powered. a hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an opto- isolator. see figures 5 and 6. 26 i fb c active-high, logic level input that can be used to indicate when the converter controlled by pup c is fully powered. a hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an opto- isolator. see figures 5 and 6. 27 i fb b active-high, logic level input that can be used to indicate when the converter controlled by pup b is fully powered. a hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an opto- isolator. see figures 5 and 6. 28 i fb a active-high, logic level input that can be used to indicate when the converter controlled by pup a is fully powered. a hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an opto- isolator. see figures 5 and 6. smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 6 package and pin configuration 21 20 19 18 17 16 15 28 27 26 25 24 23 22 vgate_hs 5v_cap drain sense feed a feed b slew_cntl en/ts fb a fb b fb c fb d v12 vgate a vgate b 8 9 10 11 12 13 14 pup c pup d fault# vss cbsense uv ov 1 2 3 4 5 6 7 pd0 pd1 reset# scl sda pup a pup b figure 3a - 28 pin qfn 21 20 19 18 17 16 15 28 27 26 25 24 23 22 vgate_hs 5v_cap drain sense feed a feed b slew_cntl en/ts ov uv cbsense fb d v12 vgate a vgate b 8 9 10 11 12 13 14 pup c pup d fault# vss 1 2 3 4 5 6 7 fb c fb b fb a pd0 pd1 reset# scl sda pup a pup b figure 3b - 28 pin soic smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 7 absolute maximum ratings temperature under bias ................ ?55c to 125c power supply current (i dd ) ............................ 15 ma storage temperature ...................... ?65c to 150c lead solder temperature (10 seconds) ......... 300c terminal voltage with respect to v ss : 5v_cap............................................. -0.3 to +7v v12, sda, scl, uv, ov, cbsense, , en/ts, fault#, ......................................... ?0. 3 to +15v vgate_hs, vgate a , vgate b pup a , pup b , pup c , and pup d ..................... -0.3 to v12+0.7v pd1, pd0, fb a , fb b , fb c , fb d , feed a , feed b , reset#, drain sense, slew_cntl . -0.3 to 5v_cap+0.7v open drain output short circuit current ...... 100ma junction temper ature ..................................... 150c esd rating per jedec ................................. 2000v latch-up testing per jede c .................. 100ma recommended operating conditions temperature range (industr ial) ......... -40c to 85c (commercial) .......... -5c to 70c supply voltage (v 12 ) (i dd = 3 ma) ............11v to 13v thermal resistance ( ja) 28-pin qfn ........ 79c/w thermal resistance ( ja) 28-pin soic ...... 80c/w moisture classification level 1 (msl 1) per j-std-020 reliability characteristics: data retentio n ................................... 100 years endurance ..................................100,000 cycles stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the dev ice at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. dc operating characteristics over recommended operating conditions, unless other wise noted. all voltages are relative to v ss . symbol parameter conditions min. typ. max. units v 12 supply voltage i 12 = 4ma 11 12 13 v i 12 supply current (1) 2 13 ma v gatehi vgate a , vgate b , vgate_hs high voltage v 12 ? v gt v 12 v v gatelo vgate a , vgate b , vgate_hs low voltage i gate = 1ma 0.1 v v sense drain sense threshold v sense = v ss 2.45 2.50 2.55 v i sense drain sense current 9 10 11 a v ents en/ts threshold 2.45 2.50 2.55 v v entshyst en/ts hysteresis 10 mv v ih 3 5 v v il reset#, pd1, pd0, scl, sda, fb a , fb b , fb c , fb d ?0.1 2 v v ol fault#, pup a , pup b , pup c , pup d i ol = 3ma 0 0.4 v i il scl, sda, cbsense, en/ts, fb a , fb b , fb c , fb d v il = v ss 1 a i il (pd) pd1, pd0 v il = v ss 10 a i ih (reset#) reset# v ih = 5v_cap 10 a v gt vgate_hs threshold 1.5 2.5 4 v notes: 1 - this value is set by the r d resistor (see page 22, dropper resistor selection). smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 8 dc operating characteristics ( continued ) over recommended operating conditions, unless other wise noted. all voltages are relative to v ss . dc programmable functions (note 2) symbol parameter conditions min. typ. max. units v uv under-voltage threshold default 2.864v -5 v uv +5 % v uvhys under-voltage hysteresis default 160mv -5 v uvhys +5 % v ov over-voltage threshold default 3.072v -5 v ov +5 % v ovhys over-voltage hysteresis default 160mv -5 v ovhys +5 % v cb circuit breaker threshold default 50mv -5 v cb +5 % v cbmax circuit breaker threshold max default 256mv -5 v cbmax +5 % v cr current regulation level default v cb +25% -5 v cr +5 % v qcb programmable quick trip circuit breaker threshold voltage default 100mv -5 v qcb +5 % i vghs_max vgate_hs maximum current default 72 a v gate = 5v ?5 i vghs_max +5 % i vgatea/b programmable i vgatea , i vgateb default 50 a ?25 i vgatea/b 25 % i feed_sel programmable feed current of the selected feed (a or b) default 18 a ?5 i feed_sel 5 % i feed_unsel programmable feed current of the unselected feed (a or b) default 26 a ?5 i feed_unsel 5 % notes: 2 - default values listed; refer to the configurat ion registers description for the range of values allowed. smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 9 ac operating characteristics over recommended operating conditions, unless other wise noted. all voltages are relative to v ss . symbol parameter conditions min. typ. max. units t qtsd quick trip shutdown fig 10, 10% overdrive to start of vgate_hs turn-off 200 ns ac programmable functions (note 2) symbol parameter conditions min. typ. max. units t cbd programmable over-current glitch filter default 40 s (2) -15 t cbd +15 % t pgd programmable power good delay default 64ms (2) -15 t pgd +15 % t cyc circuit breaker cycle mode cycle time default 5.4s (2) ?15 t cyc +15 % t puovf programmable under/over-voltage filter default 64ms (2) ?15 t puovf +15 % t pdd programmable pin detect delay default 64ms (2) ?15 t pdd +15 % t stt programmable sequence termination timer default 64ms (2) -15 t stt +15 % t glitch glitch filter default 40 s (2) -15 t glitch +15 % t pcr programmable current regulation default 64ms (2) ?15 t pcr +15 % notes: 2 - - default values listed; refer to the configurat ion registers description for the range of values allowed. smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 10 i 2 c 2-wire serial interface ac operat ing characteristics ? 100/400khz over recommended operating conditions, unless other wise noted. all voltages are relative to v ss . see figure 4 timing diagram. 100khz 400khz symbol description conditions min typ max min typ max units f scl scl clock frequency 0 100 0 400 khz t low clock low period 4.7 1.3 s t high clock high period 4.0 0.6 s t buf bus free time before new transmission - note 1 / 4.7 1.3 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:sto stop condition setup time 4.7 0.6 s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 0.2 0.9 s t dh data output hold time scl low (cycle n+1) to sda change 0.2 0.2 s t r scl and sda rise time note 1 / 1000 1000 ns t f scl and sda fall time note 1 / 300 300 ns t su:dat data in setup time 250 150 ns t hd:dat data in hold time 0 0 ns ti noise filter scl and sda noise suppression 100 100 ns t wr write cycle time memory array 5 5 ms note: 1 / - guaranteed by design. t r t f t high t low t su:sda t hd:sda t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t w r (for w rite operation only) figure 4 . basic i 2 c serial interface timing diagram for the bus interface and memory timing. the table above lists the ac timing parameters. one bit of data is transferred during each clock pulse. note that data must remain stable when the clock is high. timing diagrams smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 11 figure 5 - the smh4814 cascade sequencing the suppli es on and then monitoring for fault conditions. fb a pup a pup b pup c pup d fb b fb c fb d t pgd0 t pgd2 t pgd3 t pgd2 0 1 2 smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 14 under-/over-voltage sensing the under-voltage (uv) and over-voltage (ov) inputs provide a set of comparator s that act in conjunction with an external resistive divider ladder to sense whether or not the host supply voltage is within the user-defined limits. the power-up sequence is initiated when the input to the uv pin rises above vuv and the input to the ov pin remains below vov for a period of at least t pdd (pin detect delay time) . the t pdd filter helps prevent spurious start-up sequences while the card is being inserted. the default values for vuv and vov are 2.86v and 3.07v, respectively. this ratio allows the uv and ov input to be tied together and accommodates standard telecom over and under voltage input ranges. alternatively, vuv and vov may be programmed independently to one of four values, determined by r09[3:0]. under-/over-voltage filtering if uv falls below vuv-vuvhys or ov rises above vov for a period of time determined by the uv/ov glitch filter (r06[7:6]), the pup x and vgate x outputs may be disabled immediately. alternatively, the smh4814 can be configured so that an out-of- tolerance condition on uv or ov does not shut off the output immediately. instead, a filter delay may be inserted so that only sustained under -voltage or over-voltage conditions of longer than the filter delay time (t puovf in figure 9) can shut off the output. the uv and ov filters are enabled with bits 0 and 1, respectively, of register r0f. refer to r04[3:0] for more information on the filter delay options. figure 9 shows a sample waveform for when the under-voltage filter is enabled. uv vuv-vuvhys vgate_hs t puovf figure 9 ? example under-voltage filter timing under-/over-voltage latching by default, an out-of-tolerance condition on uv/ ov will shut off the outputs until the offending condition goes away. at that point, the entire turn on sequence may start over. however, an over or under voltage condition may also be programmed to cause a fault condition, using r0d[1:0]. in this case the fault# output is asserted, and the user is required to reset the fault condition before the device will go through another power-up sequence. under-/over-voltage hysteresis the under and over voltage comparator inputs may be configured with a programmable level of hysteresis using register r08. the falling voltage compare level may be set from 32mv to 512mv below the nominal value, in steps of 32mv. the rising voltage compare level is fixed at either vuv or vov, depending on the input. the default under and over voltage hysteresis level is set to 160mv. soft start slew rate control once all of the preconditions for powering up the dc/dc controllers have been met as explained in the previous sections, the smh4814 provides a means to soft start the external powe r mosfet. it is important to limit in-rush current to prevent damage to the add-in card or disruptions to the host power supply. applications information ( continued ) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 15 the smh4814 provides thr ee methods for controlling inrush current. the first method entails limiting the current being sourced from the vgate_hs pin. the maximum current out of this pin (i vghs_max ) is a programmable value from 8ua to 128 a (nominal), based on register r0e[3:0]. the importance of having a current-limited gate drive is that the slew rate of the load voltage is roughly equivalent to the slew rate of the fet gate to drain capacitance, once the gate to source potential has reached the fet?s threshold voltage. this slew rate (computed by dividing the gate current by the gate-drain capacitance) may be easily modified by adjusting the gate-drain capacitance, which may be a discrete component or capacitance built into the fet structure, or by adjusting the gate current. a second tool for limiting inrush current is based on further controlling the curr ent being sourced from vgate_hs. the slew_cntl pin may be used to cause the gate current to linearly ramp from 0 a to the maximum amount (described above) in the following manner. on power-up, slew_cntl is clamped at vss; when vgate_hs is enabled, slew_cntl outputs 5 a drawn from the internal 5v supply. if bit 4 of register r0e is set high, then the current out of vgate_hs is reduced by the ratio of the voltage on slew_cntl divided by 2.5v. once slew_cntl exceeds 2.5v, then the current is limited to i vghs_max . the advantage of ramping the gate current from zero up to its maximum amount is that the corresponding inrush current w ill follow a similar pattern, which may lead to less disruption to the overall system. the rate at which the gate current increases is determined by the size of the external capacitor connected to the slew_cntl pin. the third method for controlling inrush current is based on the smh4814?s current regulation feature. described in more detail in a later section, this feature regulates the current thro ugh the fet, and therefore the voltage across an external sense resistor as measured by the cbsense input, by controlling vgate_hs. normally, this operation attempts to keep cbsense from exceeding a programmable threshold voltage, v cr ; however, when the load is being initially powered, the regulation point at which cbsense is held may be gradually ramped from zero up to v cr . this feature is enabled by setting bit 5 of register r0e high, and by selecting a ratio using r0e[7:6]. in this case, cbense is regulated to the voltage on slew_cntl times the ratio determined by r0e, up to the value of v cr . the methods described her e for controlling inrush current may be used separately or together. once the voltage on slew_cntl is within a p-ch threshold voltage of 5v_cap, it must remain above this voltage. load control ? sequencing the secondary supplies the pup a through pup d output pins are used to enable the external dc/dc controllers. once the load has been fully powered, pup sequencing may begin. the smh4814 checks that two conditions have been met to indicate that the load is fully powered: 1) drain sense input voltage must be < 2.5v and 2) vgate_hs voltage must be > v 12 ? v gt . the drain sense input helps ensure that the power mosfet is not absorbing excessive steady state power from operating at a high v ds . this sensor remains active at all times (except when current regulation is enabled). the vgate sensor makes sure that the power mosfet is operating well into its saturation region before allowing the loads to be switched on. once vgate reaches v 12 ? v gt this sensor is latched. pup outputs the smh4814 has four pr ogrammable-polarity, open- drain pup (power-up permitted) outputs that may be used to control the sequencing order of dc-dc converters. after the soft start process has been completed and the load capacitance has been fully charged, there are four sequent ial time slots into which each of the pup outputs may be assigned (figure 5). a given time slot may have more than one pup output assigned to it; likewise, a time slot may have no pup outputs assigned to it. time slot 0 begins after the gate of the main soft-start fet is fully enhanced and the load is fully charged. applications information ( continued ) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 16 the duration of each time slot is programmable to one of 16 values ranging from 250 s to 768ms. when time slot 0 times out, then the pup outputs assigned to that time slot are enabled. time slot 1 begins when the affiliated feedback pins are pulled high. for example, if pup a and pup c are assigned to time slot 0, then time slot 1 begins only after pup a and pup c are enabled, and fb a and fb c are pulled high. if there are no pup outputs assigned to a given time slot, then the next time slot commences as soon as the current time slot times out. this process continues until all four time slots have timed out and all feedback pins have been pulled high. at this point, the brick sequencing is complete. the device also sequences down in the same manner (figure 6). the pupx outputs have a 12v withstand capability, so high voltages must not be connected to these pins. bipolar transistors or opto-isolators can be used to boost the withstand voltage to that of the host supply fb inputs the fbx pins are designed to receive feedback from the secondary side of the bricks and are used to indicate that an enabled brick has powered up properly. the previous section described the pup x output enabling sequence when the smh4814 receives the expected feedback from the secondary side. this section describes what happens when a fb x pin stays low or goes low unexpectedly. as described above, when a given time slot times out, the appropriate pup output is enabled. the next time slot will not commence until the associated fb pin is pulled high. the sequence termination timer (stt) is used to protect against a stalled power-on sequence. this timer commences when the pupx outputs within a given time slot are enabled, and it continues running until either all associated fbx inputs go high or the sequence termination timer times out (t stt ). if the stt times out before the appropriate fb inputs go high the device will power down the pup and vgate outputs. this control mechanism allows supplies that have dependencies based on the other voltages in the system to be cascaded properly. the status registers contai n bits that indicate the sequence has been terminated and in which sequence position the timer timed out. active fet gate control throughout the power-up process, the active-oring fet?s are kept off. current flows by means of the body diodes of those mosfet devices. once all of the pup outputs of the smh4814 have been enabled, one of the active-oring fet?s may now be enabled. initially, the feed with the lowest negative potential is the one selected to power the load. to determine the lowest supply, an on-board comparator determines which input (feed a or feed b ) is lower. since the actual feeds may both be below vss due to the drop across the body diodes, the feed a and feed b inputs are level shifted up by delivering a current across a dropper resistor (typically 100k). the feed output current is programmable from 10 a-25 a, using r07[7:4]. the vgate output corresponding to the lowest feed input is driven to v12. the feed a and feed b inputs are continually monitored for the lowest input level so that the corresponding power feed will be the one used to energize the load. however, once one of the active fet gates has been driven high, the level shifting currents being delivered out of feed a and feed b may be skewed to offer some degree of hysteresis. the current driven out of the non-selected feed is increased by anywhere from 0 to 15 a, as determined by r07[3:0]. the effect of the increased current is to make the non-selected feed appear to have an even higher potential, and thereby offering a level of hysteresis. the hysteresis will help to reduce the amount of unnecessary switching between feeds in cases where the two potential s are very close together or where there is excessive noise on the feeds. when it is determined that the selected feed is no longer the most appropriate one to power the load, the corresponding vgate output is immediately switched off via a powerful pull-down device. the complementary output is then enabled using a current limited pull-up. the amount of current is selectable from 10 a ?200 a using r05[5:4]. applications information ( continued ) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 17 circuit breaker operation the smh4814 provides a highly configurable method for detecting and controlling over-current events. a sustained over-current condition can cause physical damage to the card edge connector, the load circuitry, and may even disrupt operation of other cards in the system. to detect such ov er-current conditions, a series sense resistor (r s ) is connected between the mosfet source (which is tied to cbsense) and v ss . the board?s load current passes through the sense resistor, and the cbsense input is monitored for excessive voltage drop across r s . the smh4814 compares the cbsense input against three important voltage levels (v cb , v qcb , and v cr ) and takes appropriate action as each successive level is reached. the first voltage, v cb , is the circuit breaker trip point, which is determined by r0a[7:0]. v cb may be set to any one of 256 levels up to a maximum voltage of v cbmax , which is a configurable voltage of 128mv, 256mv, 512mv or 1024mv, as determined by r09[5:4]. for example, if v cbmax is set to 256mv, then v cb may be programmed to any value between 0 and 255mv, in 1mv increments. (refer to the register description for more information.) if cbsense exceeds v cb for a period of time longer than the glitch filter delay associated with that input, t cbd (set using r06[1:0]), then the device is considered to be in an over-current state. once in an over-current state, the smh4814 will either shut down immediately, or if the current regulation option is selected (r05[3]), the device will begin another timer. refer to the description of current regulation for more information on these actions. quick-trip tm circuit breaker the second voltage level that the cbsense input is compared against is the quick-trip? circuit breaker level, v qcb . v qcb is determined by the contents of r0b[7:0], in a manner similar to v cb . (note that the value stored in r0b is a 2?s complement number; refer to the register description for more information.) unlike the v cb comparator, the output of the v qcb comparator is a high-s peed, non-filtered signal designed to shutdown the mosfet gate very quickly. if the current regulation option is not selected, then exceeding the quick-trip level causes an immediate shutdown of the pup outputs and mosfet gate; however, if current regulation is selected, the pup outputs will not be immediately shut off. refer to the description of current regulation for more information. figure 10 shows the circuit breaker ?quick trip? response. in this figure, the voltage rises above v qcb , causing vgate to be deasserted. cbsense vgate_hs v cb t qtsd v qcb smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 20 ?48v ret. r d 6.8k ? 1/2w uv ov vss v12 smh4814 feeda feedb vgatea vgateb cbsense ? 48v a ? 48v b pupd vgate_hs drain sense v in + v out + v out - v in - on/off dc-to-dc converter a fba fbb fbc fbd primary secondary r a r shs r b pd0 pd1 pin detect 1 pin detect 0 scl sda i 2 c r 1 r 2 r 3 r ghs 10 ? r gb 10 ? r ga 10 ? v in + v out + v out - v in - on/off dc-to-dc converter b v in + v out + v out - v in - on/off dc-to-dc converter c v in + v out + v out - v in - on/off dc-to-dc converter d r t 100k ? pupa pupb pupc 100k 5v_cap 1m 1m r pd0 r pd1 r pd 100k ? r s 1k ? slew_cntl c sc 0.01 f c 5c 0.1 f figure 15a - full application schematic with all isolation components shown. the value of rd can be chosen to be a single 1/2w resistor as shown or a parallel combination of smaller 1/10w resistors as shown in figure 15b. applications information ( continued ) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 21 operating at high voltages the breakdown voltage of the external active and passive components limits the maximum operating voltage of the smh4814 hot-swap controller. components that must be able to withstand the full supply voltage are: the input and output decoupling capacitors, the protection diode in series with the drain sense pin, the power mosfet switch and the capacitor connected between its drain and gate, the high-voltage transistors connected to the power good outputs, and the dropper resistor connected to the controller?s v dd pin. over-voltage and under-voltage resistors in figure 15a, the three resistors (r1, r2, and r3) connected to the ov and uv inputs must be capable of withstanding the maximum supply voltage of several hundred volts. the resistor values should be chosen so that the uv or ov input reaches its corresponding trip point (vuv or vov) when the incoming power feed reaches its low or high operational limit. as the input impedance of uv and ov is very high, large value resistors can be used in the resistive divider. the divider resistors should be high stability, 1% metal-film resistors to keep the unde r-voltage and over-voltage trip points accurate. telecom design example a hot-swap telecom application may use a 48v power supply with a ?25% to +50% tolerance (i.e., the 48v supply can vary from 36v to 72v). the formula for calculating r1, r2, and r3 are as follows. first, a peak current, id max , must be specified for the resistive network. the value of the current is arbitrary, but it cannot be too high (self-heating in r3 becomes a problem), or too low (the value of r3 becomes very large, and leakage currents can reduce the accuracy of the ov and uv trip points). the value of idmax should be 200a for the best accuracy at the ov and uv trip points. a value of 250a for idmax is used to illustrate the following calculations. with v ov (2.864v) being the over-voltage trip point, r1 is calculated by the formula: r1 = v ov id max substituting: r1 = 2.864v 250 a = 11.46 k ? the closest standard 1% resistor value is 11.8k ? next the minimum current that flows through the resistive divider, id min , is calculated from the ratio of minimum and maximum supply voltage levels : id min = id max x v s min vs max substituting: id min = 72 v 250 a x 36 v = 125 ? now the value of r3 is calculated from id min : r3 = vs min x v uv id min v uv is the under-voltage trip point, also 2.864v. substituting: r3 = 36v x 2.864v 125 ? = 825 k ? the closest standard 1% resistor value is 825k ? then r2 is calculated: (r1 + r2) = v uv id min or ? r2 = v uv id min - r1 substituting: r2 = 2.864 v 125 ? - 11.8 k ? = 20 k ? ? 10 k ? = 11 k ? an excel spread sheet is available at: ( http://www.summitmicro.com/ ) or contact summit to simplify the resistor value calculations and tolerance analysis for r1, r2, and r3. applications information ( continued ) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 22 dropper resistor selection the smh4814 is powered from the high-voltage supply via a dropper resistor, r d . the dropper resistor must provide the smh4814 (and its loads) with sufficient operating current under minimum supply voltage conditions, but must not allow the maximum supply current to be exceeded under maximum supply voltage conditions. the dropper resistor value is calculated from: r d = v s min - vdd max i dd - i load where vs min is the lowest operating supply voltage, v ddmax is the upper limit of the smh4814 supply voltage, i dd is minimum current required for the smh4814 to operate, and i load is any additional load current from the 2.5v and 5v outputs and between v dd and v ss . calculate the minimum wattage required for rd from: p r0 (vs max - vdd min ) 2 r d where v ddmin is the lower limit of the smh4814 supply voltage, and vs max is the highest operating supply voltage. the dropper resistor value should be chosen such that the minimum and maximum i dd and v dd specifications of the smh4814 are maintained across the host supply?s valid operating voltage range. first, subtract the minimum v dd of the smh4814 from the low end of the voltage, and divide by the minimum i dd value. using this value of resistance as r d find the operating current that would result from running at the high end of the supply voltage to verify that the resulting current is less than the maximum i dd current allowed. if some range of supply voltage is chosen that would cause the maximum i dd specification to be violated, then an external zener diode with a breakdown voltage of ~12v should be used across v dd . as an example of choosing the proper r d value, assume the host supply voltage ranges from 36 to 72v. the largest dropper resistor that can be used is: (36v-11v)/3ma = 8.3k ? . next, confirm that this value of r d also works at the high end: (72v-13v)/8.3k ? = 7.08ma, which is less than 8ma. in circumstances where the input voltage may swing over a wide range ( e.g., from 20v to 100v) the maximum current may be exceeded. in these circumstances it may be necessary to add an 11v zener diode between v dd and v ss to handle the wide current range. the zener voltage should be below the nominal regulation voltage of the smh4814 so that it becomes the primary regulator. mosfet v ds (on) threshold the drain sense input on the smh4814 monitors the voltage at the drain of the external power mosfet switch with respect to v ss . when the mosfet?s v ds is below the user-defined threshold the mosfet switch is considered to be on. the v ds (on) threshold is adjusted using the resistor, r t . the v ds (on) threshold is calculated from: v ds (o n ) threshold = v sense - ( i se nse x r t ) the v ds (on) threshold varies over temperature due to the temperature dependence of i sense . the calculation below gives the v ds (on) threshold under the worst case condition of 85c ambient. using a 100k ? resistor for r t gives: v ds (on) th re shold = 2.5v - (15 a x 100 k ? ) = 1v the voltage drop across the mosfet switch and sense resistor, v dss , is calculated from: v dss = i d ( r s + r dson ) where i d is the mosfet drain current, r s is the circuit breaker sense resistor and r dson is the mosfet on resistance. applications information ( continued ) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 23 figure 15b ? atca tm application schematic applications information ( continued ) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 24 programming information i 2 c bus interface the i 2 c bus interface is a standard two-wire serial protocol that allows communication between integrated circuits. the data line (sda) is a bi- directional i/o; the clock line (scl) runs at speeds of up to 400khz. the sda line must be connected to a positive logic supply through a pull-up resistor located on the bus. start and stop conditions both the sda and scl pins remain high when the bus is not busy. data transf ers between devices may be initiated with a start condition. a high-to-low transition of the sda input while the scl pin is high is defined as a start condition. a low-to-high transition sda while scl is high is defined as a stop condition. figure 16 shows a timing diagram of the start and stop conditions. figure 16 - start and stop conditions master/slave protocol the master/slave protocol defines any device that sends data onto the bus as a transmitter, and any device that receives data as a receiver. the device controlling data transmission is called the master, and the controlled device is called the slave. in all cases the smh4814 is referred to as a slave device since it never initiates any data transfers. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during clock high time, because a change on the data line while scl is high is interpreted as either a start or a stop condition. acknowledge data is always transferred in bytes. acknowledge (ack) is used to indicate a successful data transfer. the transmitting device releases the bus after transmitting eight bits. during the ninth clock cycle the receiver pulls the sda line low to acknowledge that it received the eight bits of data. this is shown by the ack callout in figure 17. when the last byte has been transferred to the master during a read of the smh4814, the master leaves sda high for a not acknowledge (nack) cycle. this causes the smh4814 part to stop sending data, and the master issues a stop on the clock pulse following the nack. figure 17 shows the acknowledge timing. figure 17 - acknowledge timing read and write the first byte from a master is always made up of a 7- bit slave address and the read/write (r/w) bit. the r/w bit tells the slave whet her the master is reading data from the bus or writing data to the bus (1 = read, 0 = write). the first four of the seven address bits are called the device type identifie r (dti). in the case of the smh4814, the next two bits are bus address values , used to distinguish multiple devices on a common bus. the seventh bit of the slave address represents the ninth bit of the word address. the smh4814 issues an acknowledge after recognizing a start condition and its dti. figure 18 shows an example of a typical master address byte transmission. i 2 c 2-wire serial interface smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 25 figure 18 - typical master address byte transmission during a read by the mast er device, the smh4814 transmits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowledge is detected, and no stop condition is generated by the master, the smh4814 continues to transmit data. if an acknowledge is not detected (nack), the smh4814 terminates any subsequent data transmission. the read transfer protocol on sda is shown in figure 19. figure 19 - read protocol during a master write, the smh4814 receives eight bits of data, then generates an acknowledge signal. it device continues to generate the ack condition on sda until a stop condition is generated by the master. the write transfer protocol on sda is shown in figure 20. figure 20 - write protocol random access read random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condition and the slave address field (with the r/w bit set to write) followed by the address of the word it is to read. this procedure sets the internal address counter of the smh4814 to the desired address. after the word address acknowledge is received by the master, it immediately reissues a start condition followed by another slave addr ess field with the r/w bit set to read. the smh4814 responds with an acknowledge and then transmits the 8 data bits stored at the addressed location. at this point, the master sets the sda line to nack and generates a stop condition. the smh4814 discontinues data transmission and reverts to its standby power mode. sequential reads sequential reads can be initiated as either a current address read or a random ac cess read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read). however, the master now responds with an acknowledge, indicating that it requires additional data from the smh4814. the smh4814 continues to output data for each acknowledge received. the master sets the sda line to nack and generates a stop condition. during a sequential read operation the internal address counter is automatically incremented with each acknowledge signal. for read operations all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address the address counter rolls over and the memory continues to output data. i 2 c 2-wire serial interface ( continued ) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 26 figure 21 - typical ee memory write and random read operations register access the smh4814 contains a 2-wire bus interface for register access as explained in the previous section. this bus is highly configurable, while maintaining the industry standard protocol. the smh4814 responds to one of two selectable device type addresses: 1010 bin , generally assigned to nv-memories and the default address for the smh4814, or 1011 bin . the device type address is assigned by programming bit 3 of register 0x0f. the configuration registers may be locked out by setting bit 5 of register 0x0f high. this is a one-time, non-reversible operation. the smh4814 has two virtual address pins, a[2:1] (set with r0f[7:6]), associated with the 2-wire bus. the smh4814 can be configured to respond to: 1. only to the proper serial data string of the device type address and specific bus addresses (register 0x 0f, bit 4 cleared). 2. the device type address and any bus address (register 0x0f, bit 4 set). slave address bus address register type 1001 bin a2 a1 0 command and status registers, a2 a1 0 2-k bits of general-purpose memory 1010 bin or 1011 bin a2 a1 1 configuration registers table 2 - address bytes used by the smh4814. i 2 c 2-wire serial interface (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 27 s t a r t 1 a 2 bus address w a c k master slave a c k 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 1 figure 23 ? configuration register byte write s t a r t 1 a 2 bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t 1 r a c k a 2 bus address 1 1 s a 0 0 1 a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a 1 figure 25 - configurat ion register read i 2 c programming information (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 28 s t a r t 1 bus address w a c k master slave a c k 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 0 a 2 a 1 figure 28 ? general purpose memory byte write s t a r t 1 w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t 1 r a c k 1 s a 0 0 a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) bus address a 2 bus address 0 a 2 0 / 1 0 a 1 figure 30 - general purpose memory read i 2 c programming information (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 29 s t a r t w a c k master slave a c k command register address 0 0000000 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 1 0 0 1 a 2 bus address a 1 0 figure 31 ? command register write s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) status register address 0 0000010 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) 1 0 0 1 a 2 bus address a 1 0 1 0 0 1 a 2 bus address a 1 a 0 figure 32 - status register read i 2 c programming information (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 30 the end user can obtain the summit smx3200 programming system for device prototype development. the smx3200 system consists of a programming dongle, cable and windows tm gui software. it can be ordered on the website or from a local representative. the latest revisions of all software and an application brief describing the smx3200 is available from the website ( www.summitmicro.com ). the smx3200 programming dongle/cable interfaces directly between a pc?s par allel port and the target application. the device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. the windows gui software w ill generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the smh4814 via the programming dongle and cable. an example of the connection interface is shown in figure 34. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this w ill ensure proper device operation in the end application. development hardware & software pin 9, 5v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200 interface cable connector 9 7 5 3 1 10 8 6 4 2 smh4814 sda scl v12 vss 0.1 f -48v rtn (0v) -48v d1 1n4148 rd figure 34? smx3200 programmer i 2 c serial bus connections to program the smh4814. caution: damage may occur when connecting the dongle to a system utilizing an earth-connected positive terminal. smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 31 configuration registers: there are 20 user programmable configuration registers in the smh4814. the following tables describe the configuration re gister bits in detail. in cases where a timer is used, refer to the timers table 3 for a description of the codes required for each timeout selection. table 3 - timers all timers may be configured to one of the following sixteen choices: bit code timer (ms) bit code timer (m s) bit code timer (ms) bit code timer (ms) 0000 0.25 0100 16 1000 64 1100 256 0001 2 0101 24 1001 96 1101 384 0010 8 0110 32 1010 128 1110 512 0011 12 0111 48 1011 192 1111 768 register r00 ? initial current regulation and pd power-on delay. bits d[7:4] control the initial current regulation timer (def ines the amount of time current regulation is allowed during initial power-on). bits d[3:0] control the pin detect delay (defines the time from when the pd?s are enabled and uv & ov are valid until vgate_hs is allowed to turn on) register r00 d7 d6 d5 d4 d3 d2 d1 d0 action 1 0 0 0 x x x x initial current regulation timer ? 64ms, see table 3 x x x x 1 0 0 0 pin detect delay ? 64ms, see table 3 register r01 ?sequence position. bits d[7:4] control the time slot 1 (tim e from fb high to second pup allowed to go active). bits d[3:0] control the time slot 0, which is the time from when the fet is fully on to when the first pup goes active. register r01 d7 d6 d5 d4 d3 d2 d1 d0 action 1 0 0 0 x x x x time slot 1 - time from fb x high to second pup x allowed to go active? 64ms, see table 3 x x x x 1 0 0 0 time slot 0 - time from fb x high to first pup x allowed to go active ? 64ms, see table 3 configuration registers smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 32 register r02 ?time slots. bits d[7:4] control the time slot 1 (tim e from fb high to second pup allowed to go active). bits d[3:0] control the time slot 0 (time from fet fully on to first pup allo wed to go active). see timer table for bit codes. register r02 d7 d6 d5 d4 d3 d2 d1 d0 action 1 0 0 0 x x x x time slot 3 - time from fb x high to fourth pup x allowed to go active ? 64ms, see table 3 x x x x 1 0 0 0 time slot 2 - time from fb x high to third pup x allowed to go active ? 64ms, see table 3 register r03 ?duty cycle and sequence termination timers. bits d[7:4] control the duty cycle timer (restart time after fault; short circuit detect cycle time; multiply standard times by 28x). bits d[3:0] control the sequen ce termination timer (defines time fr om pup active until fb must go high). register r03 d7 d6 d5 d4 d3 d2 d1 d0 action 1 0 1 1 x x x x duty cycle timer ? defines the time between when a fault occurs and the device attempts to restart the power up sequence. note that these times are actually 28x of that listed in the table. x x x x 1 0 0 0 sequence termination timer ? time from when a pup is enabled until its corresponding fb input must go high ? 64ms, see table 3 register r04 ?current regulation and uv/ov filter timers. bits d[7:4] control the subsequent cu rrent regulation timer (except for initia l power on). bits d[3:0] control the uv/ov filter timer (when enabled). register r04 d7 d6 d5 d4 d3 d2 d1 d0 action 1 0 0 0 x x x x current regulation timer ? defines the amount of time that the fet can be held in the linear region to regulate current to the load ? 64ms, see table 3 x x x x 1 0 0 0 uv/ov filter time ? defines the length of time that an under or over voltage condition must be sustained to trip the sensor ? 64ms, see table 3 configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 33 register r05 ? pull-downs, pull-ups, current regulation and fault latch. bits d[7:6] control the fast pull down level by the number of diodes connect ed in series with the gate pull-down transistor of the quick trip sensor. bits d[5:4] contro l the gatea/gateb pull-up current. bit d[3] controls the current regulation. bit d[2] controls the fault latches off versus duty cycle. bits d[1:0] control the drain sense glitch filter. register r05 d7 d6 d5 d4 d3 d2 d1 d0 action 0 0 - - - - - - fast pull down level - no diodes connected in series with the gate pull-down transistor of the quick trip sensor. 0 1 - - - - - - fast pull down level ?1 diode connected in series with the gate pull-down transistor of the quick trip sensor. 1 0 - - - - - - fast pull down level - 2 diodes connected in series with the gate pull-down transistor of the quick trip sensor. 1 1 - - - - - - fast pull down level ? 3 diodes connected in series with the gate pull-down transistor of the quick trip sensor. - - 0 0 - - - - vgatea/vgateb pull-up current 10 a - - 0 1 - - - - vgatea/vgateb pull-up current 50 a - - 1 0 - - - - vgatea/vgateb pull-up current 100 a - - 1 1 - - - - vgatea/vgateb pull-up current 200 a) - - - - 0 - - - enable current regulation. - - - - 1 - - - disable current regulation. - - - - - 0 - - fault condition must be manually cleared - - - - - 1 - - fault cleared after duty cycle timeout - - - - - - 0 0 drain sense glitch filter is 1 s. - - - - - - 0 1 drain sense glitch filter is 14 s. - - - - - - 1 0 drain sense glitch filter is 40 s. - - - - - - 1 1 drain sense glitch filter is 119 s. configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 34 register r06 ? glitch filters. bits d[7:6] control the uv/ov glitch filter. bits d[5:4] control the reset# glitch filter. bits d[3:2] control the fbx glitch filter. bits d[1:0] cont rol the cbsense glitch filter. register r06 d7 d6 d5 d4 d3 d2 d1 d0 action 0 0 - - - - - - uv/ov glitch filter is 1 s. 0 1 - - - - - - uv/ov glitch filter is 14 s. 1 0 - - - - - - uv/ov glitch filter is 40 s. 1 1 - - - - - - uv/ov glitch filter is 119 s. - - 0 0 - - - - reset# glitch filter is 1 s. - - 0 1 - - - - reset# glitch filter is 14 s. - - 1 0 - - - - reset# glitch filter is 40 s. - - 1 1 - - - - reset# glitch filter is 119 s. - - - - 0 0 - - fbx glitch filter is 1 s. - - - - 0 1 - - fbx glitch filter is 14 s. - - - - 1 0 - - fbx glitch filter is 40 s. - - - - 1 1 - - fbx glitch filter is 119 s. - - - - - - 0 0 cbsense glitch filter is 1 s. - - - - - - 0 1 cbsense glitch filter is 14 s. - - - - - - 1 0 cbsense glitch filter is 40 s. - - - - - - 1 1 cbsense glitch filter is 119 s. register r07 ? feeda/b current. bits d[7:4] control the feed offset current. bi ts d[3:0] control the f eed hysteresis current register r07 d7 d6 d5 d4 d3 d2 d1 d0 action 1 0 0 0 x x x x feed offset current is def ined by the value in this register, plus 10 ua. the range of offset current is 10-25ua. the default value shown here represents 18ua (8b+10). x x x x 1 0 0 0 feed hysteresis current ranges from 0-15ua. the default shown here is 8ua configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 35 register r08 ? ov/uv hysteresis. bits d[7:4] control the ov hysteresis voltage level. bits d[4:0] co ntrol the uv hysteresis voltage level. register r08 d7 d6 d5 d4 d3 d2 d1 d0 action 0 1 0 0 x x x x ov hysteresis = ((n+1)*32), where n is the value stored in bits 7:4. ov hystersis ranges from 32mv to 512mv, with a default value (shown here) of 160mv x x x x 0 1 0 0 uv hysteresis = ((n+1)*32), where n is the value stored in bits 7:4. uv hystersis ranges from 32mv to 512mv, with a default value (shown here) of 160mv register r09 ? current regulation offsets, current dac max and ov/uv reference voltage bits d[7:6] control the current regulation offset. bits d[5:4] control the current dac max voltage. bits d[3:2] control the ov reference voltage range. bits d[1: 0] control the uv reference voltage range. register r09 d7 d6 d5 d4 d3 d2 d1 d0 action 0 0 - - - - - - current regulation offset is 12.5% (this is the percentage above the over current trip point at which current is re g ulated ) 0 1 - - - - - - current regulation offset is 25% 1 0 - - - - - - current regulation offset is 50% 1 1 - - - - - - current regulation offset is 100% - - 0 0 - - - - current dac max voltage is 128mv - - 0 1 - - - - current dac max voltage is 256mv (default) - - 1 0 - - - - current dac max voltage is 512mv - - 1 1 - - - - current dac max voltage is 1.024v - - - - 0 0 - - ov reference is 2.048v - - - - 0 1 - - ov reference is 2.864v - - - - 1 0 - - ov reference is 3.072v - - - - 1 1 - - ov reference is 4.096v - - - - - - 0 0 uv reference is 2.048v - - - - - - 0 1 uv reference is 2.864v - - - - - - 1 0 uv reference is 3.072v - - - - - - 1 1 uv reference is 4.096v configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 36 register r0a ? over current level bits d[7:0] control t he over current level. register r0a d7 d6 d5 d4 d3 d2 d1 d0 action 0 0 1 1 0 0 1 0 over current level = current dac max voltage (r09[5:4]) * n/256, where n is the value in this register. the default value (shown here) is 50mv register r0b ? quick-trip tm over current level. bits d[7:0] control the fast response over current level register r0b d7 d6 d5 d4 d3 d2 d1 d0 action 1 0 0 1 1 1 0 0 fast response over current level (2?s complement) = current dac max voltage * (256-n)/256. the default value (shown here) is 100mv. register r0c ? pup x sequence time slot bits d[7:6] control the pup d time slot. bits d[5:4] control the pup c time slot. bits d[3:2] control the pup b time slot. bits d[1:0] control the pup a time slot. register r0c d7 d6 d5 d4 d3 d2 d1 d0 action 0 0 - - - - - - pup d time slot = 0 0 1 - - - - - - pup d time slot = 1 1 0 - - - - - - pup d time slot = 2 1 1 - - - - - - pup d time slot = 3 - - 0 0 - - - - pup c time slot = 0 - - 0 1 - - - - pup c time slot = 1 - - 1 0 - - - - pup c time slot = 2 - - 1 1 - - - - pup c time slot = 3 - - - - 0 0 - - pup b time slot = 0 - - - - 0 1 - - pup b time slot = 1 - - - - 1 0 - - pup b time slot = 2 - - - - 1 1 - - pup b time slot = 3 - - - - - - 0 0 pup a time slot = 0 - - - - - - 0 1 pup a time slot = 1 - - - - - - 1 0 pup a time slot = 2 - - - - - - 1 1 pup a time slot = 3 configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 37 register r0d ? power down or forced shutdown, fault or no fault these bits control how the giv en inputs affect the power off. register r0d d7 d6 d5 d4 d3 d2 d1 d0 action 0 - - - - - - - fb low w/ fet on: power down 1 - - - - - - - fb low w/ fet on: forced shutdown - 0 - - - - - - ents low w/ fet on: power down - 1 - - - - - - ents low w/ fet on: forced shutdown - - 0 - - - - - ov condition: power down - - 1 - - - - - ov condition: forced shutdown - - - 0 - - - - uv condition: power down - - - 1 - - - - uv condition: forced shutdown - - - - 0 - - - fb low w/ fet on: don?t set fault - - - - 1 - - - fb low w/ fet on: set fault - - - - - 0 - - ents low w/ fet on: don?t set fault - - - - - 1 - - ents low w/ fet on: set fault - - - - - - 0 - ov condition: don?t set fault - - - - - - 1 - ov condition: set fault - - - - - - - 0 uv condition: don?t set fault - - - - - - - 1 uv condition: set fault register r0e ? slew rate control bits d[7:6] control the pup d time slot. bits d[5:4] control the pup c time slot. bits d[3:2] control the pup b time slot. bits d[1:0] control the pup a time slot. register r0e d7 d6 d5 d4 d3 d2 d1 d0 action 0 0 - - - - - - scale factor slew_cntl to curr. reg. = 1/100 0 1 - - - - - - scale factor slew_cntl to curr. reg. = 1/50 1 0 - - - - - - scale factor slew_cntl to curr. reg. = 1/20 1 1 - - - - - - scale factor slew_cntl to curr. reg. = 1/10 - - 0 - - - - - use slew_cntl for current regulation voltage = curr. reg. voltage is fixed by registers r09 and r0a - - 1 - - - - - use slew_cntl for current regulation voltage = curr. reg. voltage = slew cntl*scale factor d[7:6] - - - 0 - - - - use slew_cntl for fet gate current ramp = fet gate current is fixed at max current - - - 1 - - - - use slew_cntl for fet gate current ramp = fet gate current = (max current)*(slew cntl)/2.5 - - - - 1 1 1 1 max fet gate current = (8+(n x 8)) a largest fet gate current = (8+(15 x 8)) = 136 a - - - - 0 0 0 0 lowest fet gate current = (8+(0 x 8)) = 8 a - - - - 1 0 1 1 fet gate current = (8+(11 x 8)) = 96 a configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 38 register r0f ? interface control register r0f d7 d6 d5 d4 d3 d2 d1 d0 action 0 - - - - - - - virtual bus address a2 = 0 1 - - - - - - - virtual bus address a2 = 1 - 0 - - - - - - virtual bus address a1 = 0 - 1 - - - - - - virtual bus address a1 = 1 - - 0 - - - - - configuration lockout = unlocked - - 1 - - - - - configuration lockout = locked - - - 0 - - - - respond to only respond to virtual bus address match - - - 1 - - - - respond to all bus addresses - - - - 0 - - - slave address = 1010 - - - - 1 - - - slave address = 1011 - - - - - 0 - - enable pd?s = disabled - - - - - 1 - - enable pd?s = enabled - - - - - - 0 - enable ov filter delay = disabled - - - - - - 1 - enable ov filter delay = enabled - - - - - - - 0 enable uv filter delay = disabled - - - - - - - 1 enable uv filter delay =-enabled configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 39 register r10 ? power down or forced shutdown, fault or no fault . register r10 d7 d6 d5 d4 d3 d2 d1 d0 action 0 0 - - - - - - shorted fet detection disabled 0 1 - - - - - - shorted fet sets fault 1 0 - - - - - - shorted fet causes power down 1 1 - - - - - - shorted fet causes forced shutdown - - 0 0 - - - - blown fuse detection disabled - - 0 1 - - - - blown sets fault - - 1 0 - - - - blown causes power down - - 1 1 - - - - blown causes forced shutdown - - - - 0 - - - enable fuse check high (works in conjunction with r10 d[5:4]) - - - - 1 - - - disable fuse check high (works in conjunction with r10 d[5:4]) - - - - - 0 - - disable periodic fuse checking - - - - - 1 - - enable periodic fuse checking - - - - - - 0 0 short circuit level = 256v (defines the amount drain sense has to move during short detect) - - - - - - 0 1 short circuit level = 512v (defines the amount drain sense has to move during short detect) - - - - - - 1 0 short circuit level = 1.024v (defines the amount drain sense has to move during short detect) - - - - - - 1 1 short circuit level = 2.048v (defines the amount drain sense has to move during short detect) register r11 ? pup polarity, power-up command. . register r11 d7 d6 d5 d4 d3 d2 d1 d0 action 0 - - - - - - - command not required for power-up 1 - - - - - - - command is required for power-up - 0 0 0 - - - - power up/down configuration - - - - 0 - - - pup d polarity = active low - - - - 1 - - - pup d polarity = active high - - - - - 0 - - pup c polarity = active low - - - - - 1 - - pup c polarity = active high - - - - - - 0 - pup b polarity = active low - - - - - - 1 - pup b polarity = active high - - - - - - - 0 pup a polarity = active low - - - - - - - 1 pup a polarity = active high configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 40 register r12 ? write protect and write lockout, feedback pin control settings. register r12 d7 d6 d5 d4 d3 d2 d1 d0 action 0 0 - - - - - - not used - - 0 - - - - - set wp on power-up (0-don?t set wp; 1-set wp) - - 1 - - - - - set wp on power-up (0-don?t set wp; 1-set wp) - - - 0 - - - - write lockout = allows writes to the config or memory) - - - 1 - - - - write lockout = prevents writes to the config or memory - - - - 0 - - - fbd enable = disable pin input - - - - 1 - - - fbd enable = enable pin input - - - - - 0 - - fbc enable = disable pin input - - - - - 1 - - fbc enable = enable pin input - - - - - - 0 - fbb enable = disable pin input - - - - - - 1 - fbb enable = enable pin input - - - - - - - 0 fba enable = disable pin input - - - - - - - 1 fba enable = enable pin input fault/status registers the following tables describe the 24 bits within the fault/s tatus registers. when bit 7 of register 0x04 (slave address 1001) is low, then the data with in these registers repres ents the real-time state of the part. when bit 7 is high, then these registers represent data that was latch ed at the time that the fault occurred. there are three status/fault registers, acce ssed at slave address 1001 with address bit a8 set low, at word address 0x02-0x04. register 0x02 bit # description regsiter 0x03 bit # description regsiter 0x04 bit # description 7 pup d 7 gateb off 7 fault register is latched 6 pup c 6 gatea off 6 write protect status 5 pup b 5 over-current fault 5 reserved 4 pup a 4 fet is on 4 reserved 3 fb d 3 ents fault 3 fb fault 2 fb c 2 pd fault 2 reserved 1 fb b 1 ov fault 1 reserved 0 fb a 0 uv fault 0 reserved configuration registers (continued) smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 41 default configuration regis ter settings ? smh4814nc-184 register contents register contents r00 88 r0a 32 r01 88 r0b 64 r02 88 r0c e4 r03 b8 r0d f8 r04 88 r0e 78 r05 56 r0f 12 r06 aa r10 02 r07 88 r11 00 r08 44 r12 0f r09 59 rc1 the default device ordering number is smh4814nc-184, is programmed as described above and tested over the commercial temperature range. smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 42 packaging 28 pad qfn smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 43 packaging 28 pin soic smh4814 preliminary information summit microelectronics, inc 2080 2.0 07/21/05 44 part marking summit smh4814n ayyww annn summit part number date code (yyww) lot tracking code (summit use) drawing not to scale xx status tracking code (blank, ms, es, 01, 02,...) (summit use) product tracking code (summit use) part number suffix (contains customer specific ordering requirements) pin 1 ordering information smh4814 n package n = 28 pad qfn s = 28 lead soic summit part number nnn part number suffix (see page 41) customer specific requirements are contained in the suffix such as hex code, hex code revision, etc. c temp range c=commercial blank=industrial notice note 1 - note 1 - this is a preliminary information data sheet that describes a summit product currently in pre-production with limited characterization. summit microelectronics, inc. reserves the right to make changes to the products pr oposed in this publication. summit microele ctronics, inc. assumes no responsibility for the use of any circuits descri bed herein, conveys no license under any patent or other right, and makes no representation that the circuits are fr ee of patent infringement. charts and schedul es contained herein re flect representative operating parameters, and may vary depending upon a user?s specific application. while the information in this publication has been carefully checke d, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failu re of either system or to significantly affect their sa fety or effectiveness. products are not authorized for use in such applications unless su mmit microelectronics, inc. receiv es written assurances, to i ts satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the us er assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. revision 2.0 - this document supersedes all previous versions. please check the summit microelectronics, inc. web site at http://www.summitmicro.com/prod_s elect/summary/smh4814/smh4814.htm for data sheet updates. ? copyright 2005 summit microelectronics, inc . programmable power for a digital world? i 2 c is a trademark of philips corporation. picmg, advancedtca, cpci and atca are trademarks of t he pci industrial computers manufacturers group (picmg). |
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